1. Field of the Invention
This invention relates to a manufacturing method of an Insulated Gate or Metal Insulator Semiconductor (abbreviated hereinafter as MIS) Field Effect Transistor (abbreviated hereinafter as FET) formed in an integrated circuit having a high integration density. More particularly, this invention relates to an improvement in doping profiles for an active region of MIS FET having a short channel length.
It is known that a short channel length in FET structure causes a fluctuation or a defect of FET characteristics with an increasing integration density. A change in such as threshhold voltage, transconductance, breakdown voltage characteristic of a drain junction, and the like is caused by a punch-through phenomenon or a hot carrier effect generated in a channel region or its vicinity of the MIS FET. This invention is intended mainly to alleviate the above hot carrier effect.
2. Description of the Prior Art
Hot carrier effect is enhanced by a strong electric field existing in a depletion layer especially near the p-n junction surface of a drain region. A part of electrons, including those generated by an impact ionization caused by a carrier electron, is accelerated toward a gate insulating film by the electric field and is trapped in the gate insulating film resulting in a change of threshhold voltage and other characteristics. In order to solve the problem in the prior art, a device technology called as Lightly Doped Drain (abbreviated as LDD) is a typical example and has been utilized.
FIGS. 1 through 4 show cross sectional views corresponding successive steps in a fabrication of LDD. In FIG. 1, a gate insulating film 3 is formed on an active region 8 of a p-type silicon substrate 2, and the active region 8 is surrounded by a field oxide layer 1 and separated from other active elements. A polysilicon layer is deposited and patterned by a conventional photolithography technology, forming a gate electrode 4.
Next, phosphorous ions (P.sup.+) or arsenic ions (As.sup.+), having a comparatively low accelerating voltage and a low dose density, are implanted in a direction shown by the arrows using the gate electrode 4 as a mask, then two n.sup.- regions 5A and 6A are formed.
Then a silicon dioxide (SiO.sub.2) layer 7 is deposited by CVD method as shown in FIG. 2. Silicon dioxide layer 7 is subjected to a Reactive Ion Etching (abbreviated as RIE), thereby the layer 7 is etched anisotropically, remaining sidewalls 7A of silicon dioxide on both sides of gate electrode 4. This is shown in FIG. 3.
And next FIG. 4 shows that the substrate is implanted with arsenic ions (As.sup.+) having a high accelerating voltage and a high dose density, forming n.sup.+ regions 5B and 6B. A source region 5 is formed by n.sup.- region 5A and n.sup.+ region 5B, and a drain region 6 is formed by n.sup.- region 6A and n.sup.+ region 6B.
In an LDD structure such as explained above, carrier electrons traveling toward drain region 6 encounter two junctions, a first p-n junction between p-type substrate and n.sup.- region 6A and a second n.sup.- -n.sup.+ junction between regions 6A and 6B. If the applied voltages for each electrode are the same, the electric field strengths near the junction surfaces are remarkably reduced compared with that formed near a p-n.sup.+ junction of the conventional MIS FET structure.
The LDD structure above disclosed requires a strict control of a doping profile and an impurity distribution. Moreover, the inside front periphery A and A' of n.sup.- regions 5A and 6A facing with each other in FIG. 4 advances into the channel region after a subsequent annealing process resulting in making an effective channel length shorter. Furthermore a cross section of the sidewall 7A in FIG. 3 generally shows a convex shape outwardly, therefore the inside profile of n.sup.+ regions 5B and 6B also changes depending on a shape of sidewalls 7A formed by RIE method. Further these two impurity regions (5A, 6A) and (5B, 6B) are affected by an ion implantation voltage and a doping amount.
Because the exact control on the above processes is rather difficult problem, further improvements have been required.
Even if the above conditions are fulfilled, an LDD structure can not avoid to involve an abrupt change of an electric field on a boundary surface between n.sup.- and n.sup.+ regions, therefore the LDD also can not avoid completely the hot carrier effect.
Another method of forming sidewalls, applying a method of spin-coating the so-called Spin On Glass (conventional name and abbreviated as SOG) or Silanol on the substrate, are disclosed in the following Japanese Patents; Tokukaisho 59-92573, by K. Mitsui, and Tokukaisho 59-47769, by Y. Wada, et al. However, a spin-coated layer utilizing liquid state coating material shows a concave shape outwardly, and lacks a thickness uniformity depending on a gate pattern or a chip location on a wafer.